Continuous Assignment Statement

/*

module Nonblocking_Assignment (addr1,addr2,wr,din,valid1,valid2,data,aout);

  input [31:0] addr1,addr2;

  input [31:0] din;

  output [31:0] data,aout;

  input valid1,valid2,wr;

  

  reg [31:0] data,aout, addr;

  reg valid;

  

  always @(addr1,addr2,wr,din,valid1,valid2) begin

     valid <= (valid1 | valid2);

     addr <= (addr1[31:0] | addr2[31:0]);

     data <= (valid & wr) ? {din[31:2],2'b11} : 32'd0;

     aout <= wr ? addr: {addr1[15:0],addr2[31:16]};

  end

  initial

     $monitor($time,"NON-BLOCKING: Values valid1=%b, valid2=%b, wr=%b, addr1=%d, addr2=%d, data=%d, aout=%d", valid1,valid2,wr,addr1,addr2,data,aout);

endmodule

*/

module Blocking_Assignment(addr1,addr2,wr,din,valid1,valid2,data,aout);

  input[31:0]addr1,addr2;

  input[31:0]din;

  output[31:0]data,aout;

  input valid1,valid2,wr;

  

  reg[31:0]data,aout,addr;

  reg valid;

  

  always@(addr1,addr2,wr,din,valid1,valid2)begin

     valid=(valid1|valid2);

     addr=(addr1[31:0]|addr2[31:0]);

     data=(valid&wr)?{din[31:2],2'b11} : 32'd0;

     aout=wr?addr:{addr1[15:0],addr2[31:16]};

     $monitor($time,"BLOCKING: Values valid1=%b, valid2=%b, wr=%b, addr1=%d, addr2=%d, data=%d, aout=%d",valid1,valid2,wr,addr1,addr2,data,aout);

  end

endmodule

 

module test;

reg valid1,valid2,wr;

reg[31:0]addr1,addr2,din;

wire[31:0]data,aout;

Blocking_Assignment Block_Assign(addr1,addr2,wr,din,valid1,valid2,data,aout);

//Nonblocking_Assignment Nonblock_Assign(addr1,addr2,wr,din,valid1,valid2,data,aout);

initial begin

  valid1=0;

  valid2=0;

  addr1=32'd12;

  addr2 = 32'd36;

  din=32'd198;

  wr = 1;

  

  #5 valid1 = 1;

  #10 valid1 = 0; valid2 = 1;

  #10 addr1 = 32'd0;addr2=32'd0;

  #5 wr = 0;

  #12 wr = 1;

end

endmodule

 

/*

ncsim> run

                   0NON-BLOCKING: Values valid1=0, valid2=0, wr=1, addr1=        12, addr2=        36, data=         X, aout=         x

                   5NON-BLOCKING: Values valid1=1, valid2=0, wr=1, addr1=        12, addr2=        36, data=         0, aout=        44

                  15NON-BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=        12, addr2=        36, data=       199, aout=        44

                  25NON-BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=        44

                  30NON-BLOCKING: Values valid1=0, valid2=1, wr=0, addr1=         0, addr2=         0, data=         0, aout=         0

                  42NON-BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=         0

ncsim: *W,RNQUIE: Simulation is complete.

*/

 

/*

ncsim> run

                   0BLOCKING: Values valid1=0, valid2=0, wr=1, addr1=        12, addr2=        36, data=         0, aout=        44

                   5BLOCKING: Values valid1=1, valid2=0, wr=1, addr1=        12, addr2=        36, data=       199, aout=        44

                  15BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=        12, addr2=        36, data=       199, aout=        44

                  25BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=         0

                  30BLOCKING: Values valid1=0, valid2=1, wr=0, addr1=         0, addr2=         0, data=         0, aout=         0

                  42BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=         0

ncsim: *W,RNQUIE: Simulation is complete.

ncsim> exit

*/

You must understand how Verilog simulators schedule events.

If procedural statements appear in different procedural blocks, there is no guarantee for the order of their execution. For example:

The above code can result in both and being 1's, as well as 0's.

However, procedural statements appearing in the same procedural block are guaranteed to execute sequentially:

The above code will result in both and being 1's.

The problem with your initial code is that the concatenation operation is outside of the body of the task, therefore there is no way the scheduler can execute it between the statements in the body of the task (because they are executed sequentially, without outside interruption).

However, once you add a sequential construct (), the simulator advances to the next time slot which allows for the concatenation assignment to be executed.

Although the code you provided works for you, it is very bad practice to write Verilog this way. Why don't do this:

answered Sep 24 '13 at 20:27

One thought on “Continuous Assignment Statement

Leave a Reply

Your email address will not be published. Required fields are marked *